Design & specifications#
If you want to know how BeagleV-Fire board is designed and what are it’s high-level specifications then this chapter is for you. We are going to discuss each hardware design element in detail and provide high-level device specifications in a short and crisp form as well.
Tip
For hardware design files and schematic diagram you can checkout BeagleV-Fire GitLab repository: https://git.beagleboard.org/beaglev-fire/beaglev-fire
Block diagram#
![System block diagram](../../../_images/system-block-diagram.webp)
Fig. 448 System block diagram#
![Power tree diagram](../../../_images/power-tree-diagram.webp)
Fig. 449 Power tree diagram#
![I2C tree diagram](../../../_images/iic-tree-diagram.webp)
Fig. 450 I2C tree diagram#
System on Chip (SoC)#
![SoC bank0](../../../_images/soc-bank0.webp)
Fig. 451 SoC bank0#
![SoC bank1](../../../_images/soc-bank1.webp)
Fig. 452 SoC bank1#
![SoC bank2](../../../_images/soc-bank2.webp)
Fig. 453 SoC bank2#
![SoC bank3](../../../_images/soc-bank3.webp)
Fig. 454 SoC bank3#
![SoC bank4](../../../_images/soc-bank4.webp)
Fig. 455 SoC bank4#
![SoC power](../../../_images/soc-power.webp)
Fig. 456 SoC power#
Power management#
![DC 5V input](../../../_images/dc-5v-input.webp)
Fig. 457 DC 5V input#
![Ideal diode](../../../_images/ideal-diode.webp)
Fig. 458 Ideal diode#
![VCC 1V0](../../../_images/vcc-1v0.webp)
Fig. 459 VCC 1V0#
![VCC 1V1](../../../_images/vcc-1v1.webp)
Fig. 460 VCC 1V1#
![VCC 1V8](../../../_images/vcc-1v8.webp)
Fig. 461 VCC 1V8#
![VCC 2V5](../../../_images/vcc-2v5.webp)
Fig. 462 VCC 2V5#
![VCC 3V3](../../../_images/vcc-3v3.webp)
Fig. 463 VCC 3V3#
![VCCA 1V0](../../../_images/vcca-1v0.webp)
Fig. 464 VCCA 1V0#
![VIO enable](../../../_images/vio-enable.webp)
Fig. 465 VIO enable#
General Connectivity and Expansion#
USB-C port#
![USB C](../../../_images/usb-c.webp)
Fig. 466 USB C#
P8 & P9 cape header pins#
![P8 cape header](../../../_images/p8-header.webp)
Fig. 467 P8 cape header#
![P9 cape header](../../../_images/p9-header.webp)
Fig. 468 P9 cape header#
![Cape header voltage level translator](../../../_images/level-translator.webp)
Fig. 469 Cape header voltage level translator#
ADC#
![16bit Delta-Sigma ADC](../../../_images/adc.webp)
Fig. 470 16bit Delta-Sigma ADC#
![ADC LDO power supply](../../../_images/adc-ldo.webp)
Fig. 471 ADC LDO power supply#
Connectivity#
Ethernet#
![Gigabit ethernet](../../../_images/gigabit-ethernet.webp)
Fig. 475 Gigabit ethernet#
Memory, Media and Data storage#
DDR memory#
![LPDDR memory](../../../_images/lpdd4.webp)
Fig. 476 LPDDR memory#
eMMC#
![EMMC flash storage](../../../_images/emmc.webp)
Fig. 477 EMMC flash storage#
microSD#
![SD Card socket](../../../_images/sdcard.webp)
Fig. 478 SD Card socket#
EEPROM#
![EEPROM](../../../_images/eeprom.webp)
Fig. 479 EEPROM#
SPI flash#
![SPI Flash](../../../_images/spi-flash.webp)
Fig. 480 SPI Flash#
Multimedia I/O#
CSI#
![CSI](../../../_images/csi.webp)
Fig. 481 CSI#
Debug#
UART debug port#
![UART debug header](../../../_images/uart-debug-header.webp)
Fig. 482 UART debug header#
JTAG debug port#
![JTAG debug header](../../../_images/jtag.webp)
Fig. 483 JTAG debug header#
Mechanical Specifications#
Parameter |
Values |
---|---|
Size |
86.38 * 54.61 * 18.8 mm |
Max heigh |
18.8 mm |
PCB Size |
86.38 * 54.6 mm |
PCB Layers |
12 Layers |
PCB Thickness |
1.6 mm |
RoHS compliant |
Yes |
Gross Weight |
106 g |
Net weight |
45.8 g |